Analog-to-digital converters (ADCs) convert analog input signals into digital representations. Many ADCs operate using a successive approximation register (SAR) technique. A SAR ADC sequentially compares an analog input voltage to various reference voltage levels generated by a digital-to-analog converter (DAC). For example, during a first clock cycle, a first bit decision relating to the most significant bit (MSB) is made based on whether the analog input voltage is greater than half the reference voltage. During the next clock cycle, another bit decision relating to the second most significant bit (MSB-1) is made based on whether the analog input voltage is greater than one quarter or three quarters of the reference voltage. The conversion procedure continues accordingly, and the DAC's output converges successively to the analog input voltage while evaluating one bit during each clock cycle.
Some SAR ADCs use a charge redistribution technique with an array of capacitors. A charge stored on the capacitors is manipulated to perform the conversion from the analog domain to the digital domain. Some SAR ADCs also include a least significant bit (LSB) capacitor that is connected to a resistor network. Various tap points along the resistor network are coupled to the LSB capacitor to generate additional bit decisions.
Because SAR ADCs typically include capacitors and resistors, voltages generated based on a reference voltage take some amount of time to settle before bit decisions can be made. The settling time of an ADC can therefore detrimentally affect its performance. Also, SAR ADCs often fix the input voltage and sequentially vary the reference voltage, which can lead to errors. Many SAR ADCs use a redundant capacitor approach for error correction, but there is no way of knowing the point where a comparator has to make a critical decision for a given input (and thus no way of knowing for the given input where to apply a redundant capacitor).